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cy7c4282v cy7c4292v 64k/128kx9 low voltage deep sync fifos w/ retransmit & depth expansion cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 october 18, 1999 features ? 3.3v operation for low power consumption and easy integration into low-voltage systems high-speed, low-power, first-in first-out (fifo) memories 64k x 9 (cy7c4282v) 128k x 9 (cy7c4292v) 0.35 micron cmos for optimum speed/power high-speed, near zero latency (true dual-ported memory cell), 100-mhz operation (10 ns read/write cycle times) low power ? i cc = 25 ma ? i sb = 6 ma fully asynchronous and simultaneous read and write operation empty, full, and programmable almost empty and al- most full status flags retransmit function output enable (oe ) pin independent read and write enable pins supports free-running 50% duty cycle clock inputs width expansion capability depth expansion capability through token-passing scheme (no external logic required) 64-pin 10x10 stqfp pin-compatible 3.3v solution for cy7c4282/92 functional description the cy7c4282v/92v are high-speed, low-power, first-in first- out (fifo) memories with clocked read and write interfaces. all devices are 9 bits wide. the cy7c4282v/92v can be cas- caded to increase fifo depth. programmable features include almost full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and communications buffering. these fifos have 9-bit input and output ports that are con- trolled by separate clock and enable signals. the input port is controlled by a free-running clock (wclk) and a write enable pin (wen ). retransmit and synchronous almost full/almost empty flag features are available on these devices. depth expansion is possible using the cascade input (xi ), cas- cade output (xo ), and first load (fl ) pins. the xo pin is connected to the xi pin of the next device, and the xo pin of the last device should be connected to the xi pin of the first device. the fl pin of the first device is tied to v ss and the fl pin of all the remaining devices should be tied to v cc when wen is asserted, data is written into the fifo on the rising edge of the wclk signal. while wen is held active, data is continually written into the fifo on each cycle. the output port is controlled in a similar manner by a free-running read clock (rclk) and a read enable pin (ren ). in addition, the cy7c4282v/92v have an output enable pin (oe ). the read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. clock frequencies up to 67 mhz are achievable. ff logic block diagram 4282v?1 three-state output register read control flag logic write control write pointer read pointer reset logic input register flag program register d 0 ? 8 rclk q 0 ? 8 wen wclk rs oe dual port ram array 64k x 9 128k x 9 ren expansion logic fl /rt xi /ld paf /xo ef pae paf /xo
cy7c4282v cy7c4292v 2 functional description (continued) the cy7c4282v/92v provides four status pins: empty, full, programmable almost empty, and programmable almost full. the almost empty/almost full flags are programmable to sin- gle word granularity. the programmable flags default to emp- ty+7 and full ? 7. the flags are synchronous, i.e., they change state relative to either the read clock (rclk) or the write clock (wclk). when entering or exiting the empty and almost empty states, the flags are updated exclusively by the rclk. the flags denoting almost full, and full states are updated exclusively by wclk. the synchronous flag architecture guarantees that the flags maintain their status for at least one cycle all configurations are fabricated using an advanced 0.35 cmos technology. input esd protection is greater than 2001v, and latch-up is prevented by the use of guard rings. pin configuration stqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 4282v ? 2 cy7c4282v cy7c4292v wen rs d 8 d 7 d 6 n/c n/c n/c n/c n/c n/c d 5 n/c d 2 d 4 d 3 q 5 q 4 gnd q 3 q 2 v cc q 1 q 0 gnd n/c ff oe ef n/c gnd fl /rt wclk xi /ld gnd n/c n/c n/c n/c n/c v cc n/c n/c q 7 q 8 n/c gnd q 6 d 1 d 0 n/c n/c n/c v cc paf /xo pae n/c n/c n/c n/c n/c rclk gnd ren selection guide 7c4282v/92v-10 7c4282v/92v-15 7c4282v/92v-25 maximum frequency (mhz) 100 66.7 40 maximum access time (ns) 8 10 15 minimum cycle time (ns) 10 15 25 minimum data or enable set-up (ns) 3.5 4 6 minimum data or enable hold (ns) 0 0 1 maximum flag delay (ns) 8 10 15 active power supply current (i cc ) (ma) commercial 25 25 25 industrial 30 cy7c4282v cy7c4292v density 64k x 9 128k x 9 package 64-pin 10x10 tqfp 64-pin 10x10 tqfp
cy7c4282v cy7c4292v 3 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ....................................... ? 65 c to +150 c ambient temperature with power applied .................................................... ? 55 c to +125 c supply voltage to ground potential ..........? 0.5v to v cc +0.5v dc voltage applied to outputs in high z state ..............................................? 0.5v to v cc +0.5v dc input voltage .........................................? 0.5v to v cc +0.5v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma pin definitions signal name description i/o description d 0 ? 8 data inputs i data inputs for 9-bit bus. q 0 ? 8 data outputs o data outputs for 9-bit bus. wen write enable i the only write enable when device is configured to have programmable flags. data is written on a low-to-high transition of wclk when wen is asserted and ff is high. ren read enable i enables the device for read operation. ren must be asserted low to allow a read operation. wclk write clock i the rising edge clocks data into the fifo when wen is low and the fifo is not full. when ld is asserted, wclk writes data into the programmable flag-offset register. rclk read clock i the rising edge clocks data out of the fifo when ren is low and the fifo is not empty. when ld is low, rclk reads data out of the programmable flag-offset register. ef empty flag o when ef is low, the fifo is empty. ef is synchronized to rclk. ff full flag o when ff is low, the fifo is full. ff is synchronized to wclk. pa e programmable almost empty o when pae is low, the fifo is almost empty based on the almost empty offset value pro- grammed into the fifo. pae is synchronized to rclk. pa f /xo programmable almost full/ expansion output o dual-mode pin: cascaded - connected to xi of next device. not cascaded - when paf is low, the fifo is almost full based on the almost full offset value programmed into the fifo. paf is synchronized to wclk. fl /rt first load/ retransmit i dual-mode pin: cascaded - the first device in the daisy chain will have fl tied to v ss ; all other devices will have fl tied to v cc . in standard mode or width expansion, fl is tied to v ss on all devices. not cascaded - retransmit function is available in stand-alone mode by strobing rt. xi /ld expansion in- put/load i dual-mode pin: cascaded - connected to xo of previous device. not cascaded - ld is used to write or read the programmable flag offset registers. ld must be asserted low during reset to enable standalone or width expansion operation. if programmable offset register access is not required, ld can be tied to rs directly. oe output enable i when oe is low, the fifo ? s data outputs drive the bus to which they are connect- ed. if oe is high, the fifo ? s outputs are in high z (high-impedance) state. rs reset i resets device to empty condition. a reset is required before an initial read or write operation after power-up. operating range range ambient temperature v cc [2] commercial 0 c to +70 c 3.3v + / ? 300mv industrial [1] ? 40 c to +85 c 3.3v + / ? 300mv notes: 1. t a is the ? instant on ? case temperature. 2. v cc range for commercial -10 ns is 3.3v 150 mv.
cy7c4282v cy7c4292v 4 electrical characteristics over the operating range parameter description test conditions 7c4282v/92v -10 7c4282v/92v -15 7c4282v/92v -25 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ? 1.0 ma v cc = 3.0v, i oh = ? 2.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma v cc = 3.0v, i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc 2.0 v cc 2.0 v cc v v il input low voltage ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 v i ix input leakage current v cc = max. ? 10 +10 ? 10 +10 ? 10 +10 a i ozl i ozh output off, high z current oe > v ih , v ss < v o < v cc ? 10 +10 ? 10 +10 ? 10 +10 a i cc1 [3] active power supply current com ? l 25 25 25 ma ind 30 ma i sb [4] average standby current com ? l 6 6 6 ma ind 6 ma capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 5 pf c out output capacitance 7 pf ac test loads and waveforms (-15 , -25) [6, 7] ac test loads and waveforms (-10) notes: 3. input signals switch from 0v to 3v with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum freque ncy 20 mhz, while data inputs switch at 10 mhz. outputs are unloaded. 4. all inputs = v cc ? 0.2v, except wclk and rclk (which are switching at frequency = 0 mhz). all outputs are unloaded. 5. tested initially and after any design or process changes that may affect these parameters. 6. c l = 30 pf for all ac parameters except for t ohz . 7. c l = 5 pf for t ohz . 3.0v 3.3v output r1=330 ? r2=510 ? c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 2.0v equivalentto: th venin equivalent 4282v ? 4 200 ? all input pulses 4282v ? 5 3.0v gnd 90% 10% 90% 10% 3ns 3 ns all input pulses 4282v ? 5 i/o 50 ? v cc /2 z0=50 ?
cy7c4282v cy7c4292v 5 switching characteristics over the operating range parameter description 7c4282v/92v -10 7c4282v/92v -15 7c4282v/92v -25 unit min. max. min. max. min. max. t s clock cycle frequency 100 66.7 40 mhz t a data access time 2 8 2 10 2 15 ns t clk clock cycle time 10 15 25 ns t clkh clock high time 4.5 6 10 ns t clkl clock low time 4.5 6 10 ns t ds data set-up time 3.5 4 6 ns t dh data hold time 0 0 1 ns t ens enable set-up time 3.5 4 6 ns t enh enable hold time 0 0 1 ns t rs reset pulse width [8] 10 15 25 ns t rss reset set-up time 8 10 15 ns t rsr reset recovery time 8 10 15 ns t rsf reset to flag and output time 10 15 25 ns t prt retransmit pulse width 60 60 60 ns t rtr retransmit recovery time 90 90 90 ns t olz output enable to output in low z [9] 0 0 0 ns t oe output enable to output valid 3 7 3 10 3 12 ns t ohz output enable to output in high z [9] 3 7 3 8 3 12 ns t wff write clock to full flag 8 10 15 ns t ref read clock to empty flag 8 10 15 ns t pa f clock to programmable almost-full flag 8 10 15 ns t pa e clock to programmable almost-full flag 8 10 15 ns t skew1 skew time between read clock and write clock for empty flag and full flag 5 6 10 ns t skew2 skew time between read clock and write clock for almost-empty flag and almost-full flag 10 15 18 ns notes: 8. pulse widths less than minimum values are not allowed. 9. values guaranteed by design, not currently tested.
cy7c4282v cy7c4292v 6 switching waveforms notes: 10. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. 11. t skew1 is also the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. it the time betw een the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ef may not change state until the next rclk rising edge. write cycle timing t clkh t clkl no operation t ds t skew1 t ens wen t clk t dh t wff t wff t enh wclk d 0 ? d 17 ff ren rclk 4282v ? 6 [10] read cycle timing t clkh t clkl no operation t skew1 wen t clk t ohz t ref t ref rclk q 0 ? q 17 ef ren wclk oe t oe t ens t olz t a t enh valid data 4282v ? 7 [11]
cy7c4282v cy7c4292v 7 notes: 12. the clocks (rclk, wclk) can be free-running during reset. 13. for standalone or width expansion configuration only. 14. after reset, the outputs will be low if oe = 0 and three-state if oe =1. 15. when t skew1 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew1 < minimum specification, t frl (maximum) = either 2*t clk + t skew1 or t clk + t skew1 . the latency timing applies only at the empty boundary (ef = low). 16. the first word is available the cycle after ef goes high, always. switching waveforms (continued) reset timing t rs t rsr q 0 ? q 8 rs t rsf t rsf t rsf oe =1 oe =0 ren ,wen ef ,pae ff ,paf 4282v ? 8 [12] [14] t rss ld [13] d 0 (firstvalid write) first data word latency after reset with simultaneous read and write t skew1 wen wclk q 0 ? q 8 ef ren oe t oe t ens t olz t ds rclk t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 d 0 ? d 8 4282v ? 9 t a [15] [16]
cy7c4282v cy7c4292v 8 switching waveforms (continued) data write 2 data write 1 t ens t skew1 data in output register empty flag timing wen wclk q 0 ? q 8 ef ren oe t ds t enh rclk t ref t a t frl d 0 ? d 8 data read t skew2 t frl t ref t ds t ens t enh 4282v ? 10 t ref low [15] [15] q 0 ? q 8 ren wen d 0 ? d 8 next data read data write no write data in output register full flag timing ff wclk oe rclk t a data read t skew1 t ds t ens t enh t wff t a t skew1 t ens t enh t wff data write no write t wff low 4282v ? 11 [10] [10]
cy7c4282v cy7c4292v 9 notes: 17. t skew2 is the minimum time between a rising wclk and a rising rclk edge for pae to change state during that clock cycle. if the time between the edge of wclk and the rising rclk is less than t skew2 , then pae may not change state until the next rclk. 18. pae offset= n. 19. if a read is performed on this rising edge of the read clock, there will be empty + (n ? 1) words in the fifo when pae goes low 20. if a write is performed on this rising edge of the write clock, there will be full ? (m ? 1) words of the fifo when paf goes low. 21. 64k ? m words for cy7c4282v, 128k ? m words for cy4292v. 22. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for paf to change during that clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then paf may not change state until the next wclk. switching waveforms (continued) t enh programmable almost empty flag timing wclk pae rclk t clkh t ens t clkl t ens t pae n + 1 words in fifo t enh t ens t pae ren wen t skew2 note [17] 18 19 note 4282v ? 12 note t enh programmable almost full flag timing wclk paf rclk t clkh t ens full ? m words in fifo t clkl t ens full ? (m+1)words in fifo 4282v ? 13 t enh t ens t paf ren wen t skew2 t paf [21] [22] 20
cy7c4282v cy7c4292v 10 notes: 23. clocks are free-running in this case. 24. the flags may change state during retransmit as a result of the offset of the read and write pointers, but flags will be val id at t rtr . 25. for the synchronous pae and paf flags an appropriate clock cycle is necessary after t rtr to update these flags. switching waveforms (continued) write programmable registers wclk t clkh t clkl pae offset lsb d 0 ? d 8 wen t ens paf offset msb t clk t ds t dh 4282v ? 14 pae offset msb paf offset lsb t enh ld t ens paf offset msb paf offset lsb t enh read programmable registers rclk t clkh t ens t clkl pae offset lsb q 0 ? q 15 ren t ens pae offset msb t clk unknown t a 4282v ? 15 ld retransmit timing ren /wen fl /rt t prt t rtr 4282v ? 16 ef /ff [23, 24, 25]
cy7c4282v cy7c4292v 11 architecture the cy7c4282v/92v consists of an array of 64k to 128k words of 9 bits each (implemented by a dual-port array of sram cells), a read pointer, a write pointer, control signals (rclk, wclk, ren , wen , rs ), and flags (ef , pae , paf , ff ). resetting the fifo upon power-up, the fifo must be reset with a reset (rs ) cycle. this causes the fifo to enter the empty condition sig- nified by ef being low. all data outputs (q 0 ? 8 ) go low t rsf after the rising edge of rs . in order for the fifo to reset to its default state, the user must not read or write while rs is low. all flags are guaranteed to be valid t rsf after rs is taken low. during reset of the fifo, the state of the xi /ld pin determines if depth expansion operation is used. for depth expansion op- eration, xi /ld is tied to xo of the next device. see ? depth expansion configuration ? and figure 3 . for standalone or width expansion configuration, the xi /ld pin must be asserted low during reset. there is a 0-ns hold time requirement for the xi /ld configura- tion at the rs deassertion edge. this allows the user to tie xi /ld to rs directly for applications that do not require access to the flag offset registers. fifo operation when the wen is asserted low and ff is high, data present on the d 0 ? 8 pins is written into the fifo on each rising edge of the wclk signal. similarly, when the ren is asserted low and ef is high, data in the fifo memory will be presented on the q 0 ? 8 outputs. new data will be presented on each rising edge of rclk while ren is active. ren must set up t ens before rclk for it to be a valid read function. wen must occur t ens before wclk for it to be a valid write function. an output enable (oe ) pin is provided to three-state the q 0 ? 8 outputs when oe is asserted. when oe is enabled (low), data in the output register will be available to the q 0 ? 8 outputs after t oe . if devices are cascaded, the oe function will only output data on the fifo that is read enabled. the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and underflow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0 ? 8 outputs even after additional reads occur. programming when ld is held low during reset, this pin is the load en- able (ld ) for flag offset programming. in this configuration, ld can be used to access the four 9-bit offset registers contained in the cy7c4282v/92v for writing or reading data to these registers. when the device is configured for programmable flags and both ld and wen are low, the first low-to-high transition of wclk writes data from the data inputs to the empty offset least significant bit (lsb) register. the second, third, and fourth low-to-high transitions of wclk store data in the empty offset most significant bit (msb) register, full offset lsb register, and full offset msb register, respectively, when ld and wen are low. the fifth low-to-high transition of wclk while ld and wen are low writes data to the empty lsb register again. figure 1 shows the registers sizes and default values for the various device types. it is not necessary to write to all the offset registers at one time. a subset of the offset registers can be written; then by bringing the ld input high, the fifo is returned to normal read and write operation. the next time ld is brought low, a write op- eration stores data in the next offset register in sequence. the contents of the offset registers can be read to the data outputs when ld is low and ren is low. low-to-high tran- sitions of rclk read register contents to the data outputs. writes and reads should not be performed simultaneously on the offset registers. programmable flag (pae , paf ) operation whether the flag offset registers are programmed as de- scribed in table 1 or the default values are used, the program- mable almost empty flag (pae ) and programmable almost full flag (paf ) states are determined by their corresponding offset registers and the difference between the read and write pointers. figure 1. offset register location and default values table 1. writing the offset registers ld wen wclk [26] selection 0 0 0 1 no operation 1 0 write into fifo 1 1 no operation note: 26. the same selection sequence applies to reading from the registers. ren is enabled and a read is performed on the low-to-high transition of rclk. 64k x 9 128kx 9 8 0 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) (msb) 7 7 7 7 8 0 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) (msb) 7 7 4282v ? 16 default value = 000h default value = 000h default value = 000h default value = 000h empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb)
cy7c4282v cy7c4292v 12 the number formed by the empty offset least significant bit register and empty offset most significant bit register is re- ferred to as n and determines the operation of pae . pae is synchronized to the low-to-high transition of rclk by one flip-flop and is low when the fifo contains n or fewer unread words. pae is set high by the low-to-high transition of rclk when the fifo contains (n+1) or greater unread words. the number formed by the full offset least significant bit regis- ter and full offset most significant bit register is referred to as m and determines the operation of paf . paf is synchronized to the low-to-high transition of wclk by one flip-flop and is set low when the number of unread words in the fifo is greater than or equal to cy7c4282v (64k ? m) and cy7c4292v (128k ? m). paf is set high by the low-to- high transition of wclk when the number of available mem- ory locations is greater than m. flag operation the cy7c4282v/92v devices provide four flag pins to indicate the condition of the fifo contents. all flags operate synchro- nously. full flag the full flag (ff ) will go low when device is full. write op- erations are inhibited whenever ff is low regardless of the state of wen . ff is synchronized to wclk, i.e., it is exclusive- ly updated by each rising edge of wclk. empty flag the empty flag (ef ) will go low when the device is empty. read operations are inhibited whenever ef is low, regard- less of the state of ren . ef is synchronized to rclk, i.e., it is exclusively updated by each rising edge of rclk. programmable almost empty/almost full flag the cy7c4282v/92v features programmable almost empty and almost full flags. each flag can be programmed (de- scribed in the programming section) a specific distance from the corresponding boundary flags (empty or full). when the fifo contains the number of words or fewer for which the flags have been programmed, the paf or pae will be asserted, sig- nifying that the fifo is either almost full or almost empty. see ta ble 2 for a description of programmable flags. table 2. status flags number of words in fifo ff pa f pa e ef cy7c4282v cy7c4292v 0 0 h h l l 1 to n [27] 1 to n [27] h h l h (n+1) to (65536 ? (m+1)) (n+1) to (131072 ? (m+1)) h h h h (65536 ? m) [28] to 65535 (131072 ? m) [28] to 131071 h l h h 65536 131072 l l h h notes: 27. n = empty offset (n=7 default value). 28. m = full offset (m=7 default value).
cy7c4282v cy7c4292v 13 retransmit the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. the retransmit (rt) input is active in the standalone and width expansion modes. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred and at least one word has been read since the last rs cycle. a high pulse on rt resets the internal read pointer to the first physical location of the fifo. wclk and rclk may be free running but must be disabled during and t rtr after the retransmit pulse. with every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. data writ- ten to the fifo after activation of rt are transmitted also. the full depth of the fifo can be repeatedly retransmitted. width expansion configuration word width may be increased simply by connecting the corre- sponding input control signals of multiple devices. a composite flag should be created for each of the end-point status flags (ef and ff ). the partial status flags (pae and paf ) can be detected from any one device. figure 2 demonstrates a 18-bit word width by using two cy7c4282v/92v. any word width can be attained by adding additional cy7c4282v/92v. when the cy7c4282v/92v is in a width expansion configu- ration, the read enable (ren ) control input can be grounded (see figure 2 ). in this configuration, the load (ld ) pin is set to low at reset so that the pin operates as a control to load and read the programmable flag offsets. figure 2. block diagram of 64kx9/128kx9 low-voltage deep sync fifo memory used in a width expansion configuration ff ff ef ef write clock (wclk) write enable (wen ) load (ld ) programmable(pae ) half full flag (hf ) full flag (ff ) 9 18 data in (d) reset (rs) 9 reset (rs) read clock (rclk) read enable (ren ) output enable (oe ) programmable (paf ) empty flag (ef ) 9 data out (q) 918 first load (fl ) expansion in (xi ) 4282v ? 17 first load (f l ) expansion in (xi ) 7c4282v 7c4292v 7c4282v 7c4292v
cy7c4282v cy7c4292v 14 depth expansion configuration the cy7c4282v/92v can easily be adapted to applications requiring more than 64k/128k words of buffering. figure 3 shows depth expansion using three cy7c4282v/92vs. max- imum depth is limited only by signal loading. follow these steps: 1. the first device must be designated by grounding the first load (fl ) control input. 2. all other devices must have fl in the high state. 3. the expansion out (xo ) pin of each device must be tied to the expansion in (xi ) pin of the next device. 4. ef and ff composite flags are created by oring together each individual respective flag. figure 3. block diagram of 64kx9/128kx9 low-voltage deep sync fifo memory with programmable flags used in depth expansion configuration 4282v ? 25 writeclock (wclk) writeenable (wen ) reset (rs ) ff ff ef ef xi first load (fl ) read clock (rclk) read enable (ren ) outputenable (oe ) xo ff ef xi xo v cc fl ff ef xi xo 7c4282v 7c4292v v cc fl data in (d) data out (q) wclk wen rs rclk ren oe dq 7c4282v 7c4292v wclk wen rs rclk ren oe dq wclk wen rs d rclk ren oe q fl 7c4282v 7c4292v
cy7c4282v cy7c4292v ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. document #: 38-00657-b ordering information 64k x 9 low voltage deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4282v-10asc a64 64-lead 10x10 thin quad flatpack commercial 15 cy7c4282v-15asc a64 64-lead 10x10 thin quad flatpack commercial cy7c4282v-15asi a64 64-lead 10x10 thin quad flatpack industrial 25 cy7c4282v-25asc a64 64-lead 10x10 thin quad flatpack commercial 128k x 9 low voltage deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4292v-10asc a64 64-lead 10x10 thin quad flatpack commercial 15 cy7c4292v-15asc a64 64-lead 10x10 thin quad flatpack commercial cy7c4292v-15asi a64 64-lead 10x10 thin quad flatpack industrial 25 cy7c4292v-25asc a64 64-lead 10x10 thin quad flatpack commercial package diagram 64-pin thin plastic quad flat pack (10 x 10 x 1.4 mm) a64 51-85051-a

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